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MITSUBISHI
M62352AGP
8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION M62352A is a CMOS structured semiconductor integrated ciruict integrating 12 channels of built-in D-A converters with high performance buffer operational amplifierf or each channel output. 3-wire serial interface (DI,CLK,LD) method is used for the taransfer format of digital data to allow connection with microcomputer with minimum wiring Do terminal is provided to allow cascading serial use. Built-in buffer operational amplifiers are designed to operate or full-swing in the whole voltage range from Vcc to GND for each input/output. And their higher stability for capacitive load perfectly fits in to the use for electronic volume (VCA) or the replacement for semi-variable resistor for tuning. FEATURES 12 bit serial data input (3 wire serial data transfer method, DI, CLK, LD) Corresponds to TTL input for digital input (VINH 2V, VINL 0.8V) R-2R + segment method high performance 12 channel 8 bit D-A converters 12ch buffer operational amplifiers opperating in the whole voltage range from Vcc to GND Buffer operational amplifiers with high oscillation stability for capacitive load APPLICATION Adjustment or control of industrial or home-use electronic equipments such as VTR camera, VTR set, TV, and CRT display.
Pin configuration(Top View)
VSS 1 AO3 2 AO4 3 AO5 4 AO6 5 AO7 6 AO8 7 AO9 8 AO10 9 VDD 10
20 19 18 17 16 15 14 13 12 11
GND AO2 AO1 DI CLK LD DO AO12 AO11 VCC
Outline 20P2E-A
20
19
18
17
16
15
14
13
12
11
8bit R-2R + segment D-A converter
D0
10 11
D-A
L
(12)
ch3 8bit R-2R +segment D-A converter
4
5
6
7
8
9
1 0
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MITSUBISHI
M62352AGP
8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
EXPLANATION OF TERMINALS
Pin No.
17 14 16 15 18 19 2 3 4 5 6 7 8 9 12 13 11 20 10 1
symbol DI DO CLK LD AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 VCC GND VDD VSS
Function Serial data input terminal.12bit serial data is input to this terminal. Serial data output terminal.Serial data of 12bit shift register is output from this terminal. Serial clock input terminal.Input signal from DI terminal is input to 12bit shift register upon the rise of shift clock. Data is loaded to register when 'H' is input to LD terminal.
8bit D-A converter output terminal. Built-in buffer amp.is connected to VCC. D-A converted voltage between VDD and VSS is output to each terminal.
Power supply terminal. Digital and Analog common GND D-A converter High level reference voltage input terminal. D-A converter Low level reference voltage input terminal.
BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS
VCC
11
GND
20
DI 17 CLK
16 D0 D1 D2 D3
12 BIT SHIFT REGISTER
D4 D5 D6 D7 D8 D9 D10 D11
14 DO
DECODER (8) (12)
12 345 6 7 8 9 10 11 12
15 LD
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit D-A converter
8bit D-A converter
8bit D-A converter
8bit D-A converter
8bit D-A converter
8bit D-A converter
A1
A4
A5
A10
A11
A12
10
18
19
2
9
12
13
1
VDD
AO1
AO2
AO3
AO10
AO11
AO12
VSS
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MITSUBISHI
M62352AGP
8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DIGITAL DATA FORMAT
Last LSB First MSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
DAC DATA DAC DATA
D0 0 1 0 1 : 0 1 D1 D2 0 0 1 1 : 1 1 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D6 0 0 0 1 : 1 1 D7 0 0 0 0 : 1 1
DAC SELECT DATA
D-A output (VrefU-VrefL)/256 x 1+VrefL[V] (VrefU-VrefL)/256 x 2+VrefL[V] (VrefU-VrefL)/256 x 3+VrefL[V] (VrefU-VrefL)/256 x 4+VrefL[V] : (VrefU-VrefL)/256 x 255+VrefL[V] VrefU[V] (255LSB) (256LSB)
VrefU=VDD VrefL=VSS
(1LSB) (2LSB) (3LSB) (3LSB)
DAC SELECT DATA D8 D9 D10 D11 DAC SELECTION
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don't Care A1select A2select A3select A4select A5select A6select A7select A8select A9select A10select A11select A12select Don't Care Don't Care Don't Care
TIMING CHART (model)
CLK
SI
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LD
AO1~ AO12
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MITSUBISHI
M62352AGP
8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
ABSOLUTE MAXMUM RATING
Symbol Vcc VDD VIN Vout Pd Topr Tstg Parameter Supply voltage D-A converter High levelreference voltage Digital input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ratings - 0.3 ~ 7.0 - 0.3 ~ 7.0
- 0.3 ~ VCC+0.3 - 0.3 ~ VCC+0.3
Unit V V V V mW C C
150 - 20 ~ 85 - 40 ~ 125
ELECTRIC CHARACTERISTICS
(VCC, VrefU=5V 10% , VCC VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85C unless otherwise specified.) Symbol Vcc Icc IILK VIL VIH VOL VOH Parameter Supply voltage Supply current Input leak current
Digital input Low voltage Digital input High voltage Digital output Low voltage Digital output High voltage IOL = 2.5mA IOH= - 400 A CLK=1MHz Operation
V CC =5V, IAO =0 A
Ratings Conditions MIN 4.5 TYP 5.0 1.5 -10 2.0 0.4 VCC -0.4 MAX 5.5 3.5 10 0.8 Unit V mA A V V V V
VIN=0 ~ VCC
Note: Changes from M62352GP: Digital input voltage corresponds to TTL spec.
(VCC, VrefU=5V 10% , VCC VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85C unless otherwise specified.) Symbol
IrefU
Parameter
Conditions
VrefU =5V,VrefL =0V,IAO=0 A
Data condition: at Maxmum Current
The output does not necessarily be the Values within the reference voltage setting range.The output value is determined by the buffer amplifier output voltage range(VAO).
MIN
Ratings TYP 1.4
MAX 2.5
VCC
Unit mA
Reference voltage pin current D-A converter High level VDD(V refU ) reference voltage range D-A converter Low level VSS (V refL ) reference voltage range
VAO
3.5 GND 0.1 0.2 -1 -1.0 -1.5 -2.0 -2.0 5
V
VCC -3.5 VCC-0.1 VCC-0.2
Buffer amplifier output drive range Buffer amplifier output drive range Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitative load
IAO = 100 A IAO = 500 A Upper side saturation voltage=0.3V
V
IAO
Lower side saturation voltage=0.2V
1 1.0 1.5 2.0 2.0 0.1
mA LSB LSB LSB LSB F
SDL SL
Szero
SFULL
VrefU = 4.79V VrefL = 0.95V (15mV/LSB) VCC = 5.5V without load(I AO=+0 A)
Co Ro
ohm
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MITSUBISHI
M62352AGP
8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
Symbol
tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO tLDD
(VCC, VrefU=5V 10% , VCC VrefU, GND, VrefL=0.0V, Ta=-20 ~ +85C unless otherwise specified.)
Parameter Clock "L" puise width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" hold time
Data output delay time D-A output settling time
Ratings Conditions MIN 200 200 200 30 60 200 100 100
CL 100pF CL 100pF,VAO:0.5 4.5V
The time until the output becomes the final value of 1/2 LSB
TYP
MAX
Unit ns ns ns ns ns ns ns ns
70
350 300
ns s
Measurement circuit
DUT
input
output C L 100pF
TIMING CHART
tCR tCKH tCF tCHL
CLK
tCKL tLDC
DI
tDCH tCHD tCHL tLDH
LD
tLDD
AO1~ AO12 output
tDO
t
DO
DO output
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MITSUBISHI
M62352AGP
8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
TYPICAL APPLICATION
11
10
VCC
VDD(VrefU) AO1 AO2 AO3 AO4
18 19 2 3 4 5 6 7 8 9 12 13
18 17
DI CLK LD DO
AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12
MCU
16 15
GND
20
VSS(VrefL)
1
Note: M6235 2AGP has 3 terminals(VDD, VCC, and VSS) to which constant voltage is to be applied. Ripple voltage or spike noise to these terminals may worsen converting precision or cause erroneous operations. So be sure to use this device by putting cacpacitor between each terminal and GND to get D-A conversion operation stabilized. Output buffer amplifiers have high oscillation stability against capacitive load. This means that jitters by wirings around output terminals or capcitor between output and GND(0.1uF max.) do not cause any problems with DAC operations. Connect capacitor(0.1uF or around) between output and GND for protection from spark discharge when this device is used under such high electric field as that for instance of instruments with cathode ray tube.
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